1. Field of the Invention
The present invention relates to a semiconductor device having a random access memory (RAM) in multi-chip package (MCP) products.
2. Description of the Related Art
In recent years, achievements of mass-storage and reduced semiconductor memories increase the needs for MCP products.
The dominating MCP includes a RAM such as a low-power synchronous dynamic RAM (LPSDRAM), a static RAM (SRAM), a pseudo-SRAM (PSRAM) and a fast cycle RAM (FCRAM) in combination with a non-volatile memory such as an NAND-type flash memory and an NOR-type flash memory. The above MCP makes it possible to realize a mass-storage RAM in a small space. Therefore, it has been used in a wider range from mobile instruments to supercomputers.
When a command input is given to a normal RAM, a controller generally supplies the RAM with a chip select signal for use in determination to select the RAM or not. Controlling the RAM based only on the chip select signal requires the controller to have chip select pins by the number of RAMs to provide output signals. Namely, the controller is required to have four chip select pins for four RAMs and eight chip select pins for eight RAMs. Thus, the more the number of RAMs to be mounted increases, the more the number of chip select pins of the controller increases.
In accordance with the achievement of mass-storage RAMs, plural RAMs may be replaced with a single mass-storage RAM having a two- or four-fold cell storage. In such the case, a single chip select pin is sufficient while the achievement of mass-storage RAMs requires an increased number of address pins. The achievement of mass-storage leaves undesired chip select pins on the controller. Therefore, the address pins are not designed for the achievement of mass-storage. Accordingly, every RAM replacement requires redesigning the controller and consequently causes a problem associated with increases in cost.
JP 10-240607A (Patent Document 1) discloses a MCP product-related technology associated with a memory system, which includes at least two memory units of different characteristics mounted thereon, and which is configured to switch between the memory units for use on setting a memory use environment or during a job execution. This system includes the mounted memories of different characteristics and is configured to switch between a high-speed accessible memory and a low-speed mass-storage memory for use.
JP 8-180668A (Patent Document 2) discloses a memory system, which includes a logic control element in a memory device to set each memory circuit in a selected state or a non-selected state. This system provides a logic control element in a memory device to make it possible to set each memory circuit in a selected state or a non-selected state.
Even with the Patent Documents 1 and 2, the above problem can not be solved and there designing of the controller is required if the number of memories mounted fluctuates. Namely, the production cost rises.
It is very important for RAMs for mobile instruments, typically LPSDRAMs and PSRAMs, to suppress the production cost and reduce the power consumption as well.